Date: Mon, 02 Dec 1996 15:13:03 GMT
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<title>CSE 567 Syllabus</title>

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<h1>CSE 567: Principles of Digital Systems Design </h1>
<h3>Carl Ebeling, Fall 1996 </h2>

<hr>

<H3>Syllabus</H3>
<P>
The goal of this course to give an overall understanding of how
computation is implemented in hardware.  The class starts with the
basics of implementing functional (combinational) and sequential
computations.  It builds on this to discuss methodologies for
designing and implementing large systems comprising many components.
Standard system components like memories, datapath elements and busses
are described and models for combining them to perform both general
and special-purpose computation are covered.  Topics also include
system specification using a hardware description language and
synthesis and optimization of combinational and sequential circuits.
<P>
<OL><LI> <b> Switching Algebra.</b> 3 lectures.
<UL><LI> Boolean algebra
<LI> Switching networks
<LI> Basic theorems
<LI> Canonical logic forms
</UL>
<P>
<LI> <b> Combinational Logic.</b> 5 lectures.
<UL><LI> Analysis and synthesis of combinational logic
<LI> Don't care information
<LI> Two-level and multi-level logic minimization
</UL>
<P>
<LI> <b> Sequential Logic.</b> 5 lectures.
<UL><LI> Synchronous circuits
<LI> Clocking methodologies
<LI> FSM synthesis and optimization
<LI> Synchronous vs. self-timed systems
</UL>
<P>
<LI> <b> Specification, synthesis and validation tools</b> 3 lectures
<UL><LI> Verilog hardware description language
<LI> Structural vs. behavioral specification
<LI> Simulation using Verilog-XL
<LI> Circuit synthesis using Synopsis
</UL>
<P>
<LI> <b> Regular Structures and System Components.</b> 5 lectures.
<UL><LI> Decoders, multiplexors and encoders
<LI> Shifters
<LI> Adders, ALUs and multipliers
<LI> Register files
<LI> Static and dynamic RAM design
<LI> PLAs and ROMs
<LI> Bus structures and communication
</UL>
<P>
<LI> <b> VLSI Processor Design.</b> 4 lectures.
<UL><LI> Control/Datapath model of computation
<LI> Datapath organization
<LI> Control logic alternatives
<LI> Pipelining
<LI> Retiming
</UL>
<P>
<LI> <b> Special-Purpose Computation Structures.</b> 4 lectures
<UL><LI> Custom computation
<LI> Overview of high-level synthesis
<LI> Systolic arrays
<LI> DSP computation
</UL></OL><BR>

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ebeling@cs.washington.edu
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